Heretofore, in this field, resistors have been planar polysilicon resistors. Design of these planar polysilicon resistors is a trade-off of resistance versus processing and circuit layout efficiency. Because of the relatively low resistivity of polysilicon, it is difficult to form relatively high value resistors. To form a relatively high resistance the designer will increase the length or decrease the cross-sectional area of the resistor. Increasing the length of the resistor will require additional wafer surface area to form the resistor. Decreasing the cross-sectional area, defined as the product of film thickness and width, will make processing difficult because variations in film thickness and width will have a larger influence on resistance.
Another method for providing the resistive function is to use active load transistors. The advantage of using active load transistors over using planar resistors is space savings. The difficulty with active loads is they have a limited linear range, require a biasing voltage outside the range of the signal voltage which they act upon, and their area must be significantly increased to pass larger currents.
Within the field of SRAM design, both planar resistors and active loads have been used. In early CMOS (Complementary Metal Oxide Semiconducting) SRAM designs, the six transistor (6T) memory cell design was used. This design consists of two cross-coupled n-channel transistors each with an associated active load p-channel transistor. This design also has two n-channel pass transistors for gating of the signals in or out of the cross-coupled memory cell for a total of six transistors. The difficulty with this design is the relatively large amount of wafer area needed for the six transistors. A further difficulty is the need for n-well regions to be formed within the bulk p-type material in order to fabricate the p-channel transistors. The boundary of n-well and p-well requires costly spacing to diffusions to prevent the creation of horizontal SCRs which are latch-up sensitive.
More recently, SRAM cell designs have migrated to 4 transistor cell designs which use polysilicon pull-up resistors. This design is referred to as the 4T-2R SRAM memory cell. This design uses less wafer area, but difficulties arise in keeping the polysilicon pull-up resistance sufficiently high for low power consumption. The design of the polysilicon resistors is a trade-off between wafer area, power consumption, and producibility.
Because of this difficult design trade-off, the industry has pursued stacked memory structures in which a thin film p-channel load transistor may be deposited above its associated n-channel transistor. In this manner, a three dimensional circuit fabrication has been effected. While this accomplishes a very small wafer area usage, it requires a great number of process steps. Other difficulties involve improving the grain size of the polysilicon crystal, and maintaining reproducible device parameters.